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For the execution of a computer program, it requires the synchronous working of more than one component of a computer. Usually, processors control all the process of transferring data, right from initiating the transfer to the storage of data at the destination. This adds load on the processor and most of the time it stays in the ideal state, thus decreasing the efficiency of the system. DMA controller transfers data with minimal intervention of the processor. The term DMA stands for direct memory access.
The hardware device used for direct memory access is called the DMA controller. DMA controller provides an interface between the bus and the input-output devices. Although it transfers data without intervention of processor, it is controlled by the processor.
The processor initiates the DMA controller by sending the starting address, Number of words in the data block and direction of transfer of data. More than one external device can be connected to the DMA controller.
It also contains the control unit and data count for keeping counts of the number of blocks transferred and indicating the direction of transfer of data.
When the transfer is completed, DMA informs the processor by raising an interrupt. The typical block diagram of the DMA controller is shown in the figure below. DMA controller has to share the bus with the processor to make the data transfer. The device that holds the bus at a given time is called bus master.
If the DMA controller is free, it requests the control of bus from the processor by raising the bus request signal. Processor grants the bus to the controller by raising the bus grant signal, now DMA controller is the bus master. The processor initiates the DMA controller by sending the memory addresses, number of blocks of data to be transferred and direction of data transfer.
After assigning the data transfer task to the DMA controller, instead of waiting ideally till completion of data transfer, the processor resumes the execution of the program after retrieving instructions from the stack.
It makes the data transfer according to the control instructions received by the processor. After completion of data transfer, it disables the bus request signal and CPU disables the bus grant signal thereby moving control of buses to the CPU. Then the controller requests the processor for the bus, raising the bus request signal.
After receiving the bus grant signal it transfers the data from the device. For n channeled DMA controller n number of external devices can be connected. Meanwhile, if the CPU requires the bus it has to stay ideal and wait for data transfer. It continuously issues a request for bus control, makes the transfer of one byte and returns the bus. S0- The first state, where the controller has requested for the bus and waiting for the acknowledgment from the processor.
S1, S2, S3, S4 are called the working states of the A where the actual transfer of data takes place. If more time is needed for transfer wait states SW are added between these states.
For memory —to- memory transfer read-from-memory and write-to-memory transfers have to be made. Eight states are required for single transfer. The first four states with subscripts S11, S12, S13, S14 does the read-from-memory transfer and the next four S21, S22, S23, S24 are for write-to-memory transfer.
DMA goes into the ideal state when no channel is requesting service and perform SI state. SI is an inactive state where the DMA is inactive until it receives a request. When DMA is in the ideal state and gets no further channel requests, it outputs an HRQ signal to the processor and enters into Active state where it can start the transfer of data either by burst mode, cycle stealing mode or transparent mode.
Upon receiving a transfer request the controller-. For each channel contains two bit registers — 1 DMA address register and 2 Terminal count register, which should be initialized before a channel is enabled. The address of first memory location to be accessed is loaded in the DMA address register. The lower order 14 bits of the value loaded in the terminal count register indicates the number of DMA cycles minus one before the activation of Terminal count output.
Type of operation for a channel is indicated by the most significant two bits of the Terminal count register. DMA Direct Memory Access controller is being used in graphics cards, network cards, sound cards etc… DMA is also used for intra-chip transfer in multi-core processors.
Operating in one of its three modes, DMA can considerably reduce the load of the processor. In which of the modes of DMA have you worked with? Which of the mode you consider is more effective? What is a DMA Controller?
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Direct memory access with DMA controller 8257/8237
For the execution of a computer program, it requires the synchronous working of more than one component of a computer. Usually, processors control all the process of transferring data, right from initiating the transfer to the storage of data at the destination. This adds load on the processor and most of the time it stays in the ideal state, thus decreasing the efficiency of the system. DMA controller transfers data with minimal intervention of the processor. The term DMA stands for direct memory access. The hardware device used for direct memory access is called the DMA controller. DMA controller provides an interface between the bus and the input-output devices.
Microprocessor - 8257 DMA Controller
It is designed by Intel to transfer data at the fastest rate. Then the microprocessor tri-states all the data bus, address bus, and control bus. These are the four individual channel DMA request inputs, which are used by the peripheral devices for using DMA services. When the fixed priority mode is selected, then DRQ 0 has the highest priority and DRQ 3 has the lowest priority among them. These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of their request by the CPU. These lines can also act as strobe lines for the requesting devices. These are bidirectional, data lines which are used to interface the system bus with the internal data bus of DMA controller.