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This banner text can have markup. Search the history of over billion web pages on the Internet. Gerits, L. Englisch, R. Grand Rapids, MI This book is copyrighted. No part of this book may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise without the prior written permission of Abacus Software or Data Becker, GmbH.

Every effort has been made to ensure complete and accurate information concerning the material presented in this book. However, Abacus Software can neither guarantee nor be held legally responsible for any mistakes in printing or faulty instructions contained in this book. The authors will always appreciate receiving notice of subsequent mistakes. This bit chip is in a class by itself; programmers and hardware designers alike find the chip very easy to handle.

Before the Atari ST's arrival on the marketplace, there were no affordable machines available to the home user. Now, though, with bit computers becoming more affordable to the common man, the 8-bit machines won't be around much longer. What does the have that's so special? In fact, as the price of memory drops, you'll soon be seeing based 64K machines for the same price as present-day 8-bit computers with the same amount of memory. Figure 1.

The eight data registers can store and perform calculations, as well as the normal addressing tasks. Eight-bit systems use the accumulators for this, which limits the programmer to a total of 8 accumulators. Our data registers are quite flexible; data can be handled in 1-, 8-, and bit sizes.

Even four-bit operations are possible within the limits of Binary Coded Decimal counting. When working with bit data, all 32 bits can be handled with a single operation. With 8- and bit data, only the 8th or 16th bit of the data register can be accessed. The address registers aren't as flexible for data access as are the data registers. These registers are for addressing, not calculation. Processing data is possible only with word bit and longword bit operations. The address registers must be looked at as two distinct groups, the most versatile being the registers A0-A6.

Registers A7 and A7' fulfill a special need. These registers are used as the stack pointer by the processor. Note that the two registers work "under" A7, but the register contents are only available to the respective operating mode. We'll discuss these operating modes later. The program counter is also considered a bit register. It is theoretically possible to handle an address range of over 4 gigabytes.

But the address bits AA31 aren't used, which "limits" us to 16 megabytes. The status register comprises 16 bits, of which only 10 bits are used. This status register is divided into two halves: The lower eight bits bits 0 to 4 proper is the "user byte".

These bits, which act as flags most of the time, show the results of arithmetical and comparative operations, and can be used for program branches hinging on those results. The remaining bits are unused. Bit 15 works as a trace bit, which lets you do a software controlled single-step execution of any program. Bit 13 is the supervisor bit. When this bit is set, the is in supervisor mode.

This is the normal operating mode; all commands are executed in this mode. In user mode, in which programs normally run, privileged instructions are inoperative. A special hardware design allows access into the other memory range while in user mode e.

The system byte of the status register can only be manipulated in supervisor mode; but there's a simple method of switching between modes. The has great potential for handling interrupts. Seven different interrupt priorities exist, the highest being the "non-maskable interrupt"; NMI. This interrupt recognizes when all three IPL pins simultaneously read low 0. If, however, all three IPL pins read high, there is no interrupt, and the system operates normally.

The other six priorities can be masked by appropriate setting of the system byte of the status register. For example, if bit 12 of the interrupt mask is set, while 10 and II are off, only levels 7, 6 and 5 , and are recognized. Interrupts, according to Motorola nomenclature, are an external form of an exception the machine can interrupt what it's doing, do something else, and return to the interrupted task if needed.

The distinguishes between normal operation and exception handling, rather than between user and supervisor mode. One such set of exceptions are the interrupts.

Other things which cause exceptions are undefined opcodes, and word or longword access to a prohibited address. The exception table is located here. Exceptions are all coded as one of four bytes of a longword. Encountering an exception triggers the , and the address of the corresponding table entry is output A special exception occurs on reset, which requires 8 bytes two longwords ; the first longword contains the standard initial value of the supervisor stack pointer, while the second longword contains the address of the reset routine itself.

See Chapter 3. The first group combines data and address busses. The data bus consists of pins D0-D15, and the address bus A1-A Address bit A0 is not available to the Also, the can access data located on odd addresses as well as even addresses.

The signals will be dealt with later. It's important to remember in connection with this, that by word access to memory, the byte of the odd address is treated as the low byte, and the even 7 Abacus Software Atari ST Internals address is the high byte. Word access shouldn't stray from even addresses. That means that opcodes whether all words or a single word must always be located at even addresses.

The second group of connections comprise the signals for asynchronous bus control. This indicates to memory and peripherals whether the processor is writing to or reading data from the address on the bus.

However, for individual access to the low-byte and high-byte of a word, the processor must be able to distinguish between the two bytes. Accessing the data at an odd address activates the Lower Data Strobe only, while accessing data at an even address activates the Upper Data Strobe. Bit A0 from the address bus is used in this case. After every access when the system must distinguish between three conditions word, even byte, odd byte , A0 determines how to complete the access.

If the signal is not low within a bus cycle, the address and data lines "freeze up" until DTACK turns low. This can also occur in a WAIT loop. This way, the processor can slow down memory and peripheral chips while performing other tasks. If no wait cycles are used on the ST, the processor moves "at full tilt".

A computer is more than memory and a microprocessor; interfaces to keyboard, screen, printer, etc. In most cases, interfacing is handled by special ICs, but the has a huge selection of interface chips onboard. For hardware designers we'll take a little time explaining these synchronous bus signals. The signal E also known as 02 or phi 2 represents the reference count for peripherals.

Users of and machines know this signal as the system counter. Whereas most peripheral chips have a maximum frequency of only 1 or 2 mHz, the has a working speed of 8 mHz, which can increased to 10 by the E signal.

The frequency of E in the ST is kHz. The signal VPA Valid Peripheral Address sends data over the synchronous bus, and delegates this transfer to specific sections of the chip. Without this signal, data transfer is performed by the asynchronous bus. VPA also plays a role in generating interrupts, as we'll soon see. The fourth group of signals allows simple DMA operation in the system.

DMA Direct Memory Access directly accesses the DMA controllers, which control computer memory, and which is the fastest method of data transfer within a computer system. To execute the DMA, the processor must be in an inactive state. All essential signals on the processor are made high; in particular, the data, address and control busses are no longer influenced by the processor.

The DMA controller can then place the desired address on the bus, and read or write data. The fifth group of signals on the control interrupt generation. The 's "user's choice" interrupt concept is one of its most extraordinary performing qualities; you have ! These interrupt vectors are divided into 7 non-auto-vectors and auto-vectors, plus 7 different priority lines.

The combination determines the priority of the interrupt. However, if all three lines are low, then highest priority takes over, to execute a non-maskable interrupt. All the combinations in between affect special bits in the 's status register; these, in turn, affect program control, regardless of whether or not a chosen interrupt is allowable. Wait - what are auto-vectors and non-auto-vectors? What do these terms mean? All seven interrupt codes on the IPL pins have their own vectors, though.


The Atari ST Internals

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The hardware was so similar to Apple's Macintosh at the time that with the addition of the Spectre GCR the ST was able to run Macintosh software faster than an actual Mac Plus at the time since the Atari's clock speed was higher and with a larger and higher resolution display. In fact, the Stacy the laptop version of the Atari ST was the first and only way to own a laptop running Mac OS at the time since Apple did not offer one until much later. The ST was sold with either Atari's color monitor or the less expensive monochrome monitor. The system's two color graphics modes are only available on the former while the highest-resolution mode needs the monochrome monitor. In some markets, particularly Germany , the machine gained a strong foothold as a small business machine for CAD and desktop publishing work. Thanks to its built-in MIDI ports, the ST enjoyed success for running music sequencer software and as a controller of musical instruments among amateurs and well-known musicians alike. Jay Miner , one of the original designers for the custom chips found in the Atari and Atari 8-bit family , tried to convince Atari management to create a new chipset for a video game console and computer.


Atari ST Internals


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